In recent years, in wireless communication apparatuses, such as wireless LAN apparatuses, an all digital PLL (ADPLL) circuit that converts all control signals of a phase locked loop (PLL) circuit into digital signals is used. Since the ADPLL circuit replaces an analog circuit by a digital circuit, space saving and power saving are enabled by the progress of a process.
The ADPLL circuit includes a digital loop filter, a digitally controlled oscillator (DCO), a counter, and a time-to-digital converter (TDC). The counter counts an output CKV of the DCO and outputs a count value CNTV, based on a reference signal REF synchronized with the output CKV of the DCO. The TDC extracts the phase difference d of one cycle of the output CKV of the DCO or less, in synchronization with the reference signal REF. A comparison result (difference) between a value, which is obtained by adding the count value CNTV and the phase difference d, and a phase control signal is provided to the digital loop filter. An oscillation frequency of the DCO is controlled based on an output of the digital loop filter.
When the DCO is controlled, frequency control methods of a Unary control type (for example, refer to “Mike Shuo-Wei Chen, Davis Su, Srenik Mehta “26.3 A Calibration-Free 800 MHz Fractional-N Digital PLL with Embedded TDC”, 2010 IEEE International Solid-State Circuits Conference”) and a Binary control type are used. In the Unary control type, since the number of control lines increases, consumption power and a mounting area increase. In the Binary control type, at a change point of upper bits, switching noise may be easily generated due to a variation in parasitic capacitance or a transistor characteristic.